1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and in particular, to a non-volatile semiconductor memory device having, at the prestage of an address decoder, a level shifter for generating a program voltage.
2. Description of the Related Art
Generally, in a non-volatile semiconductor memory device such as an EPROM (Erasable Programmable ROM) or an EEPROM (Electrically Erasable Programmable ROM), a floating gate type transistor is employed as a memory cell transistor. In order to write data in such a memory cell transistor, it is necessary to supply the memory cell transistor with a write-in voltage, which is higher than the readout voltage for reading the data of the memory cell transistor. For example, in a data read mode, a read-out voltage of 5 V is supplied to a control gate of the memory cell transistor. In a programming mode, a write-in voltage of 12.5 V is supplied to the control gate of the memory cell transistor.
In a conventional memory device, as shown in FIG. 1, in order to supply the voltage of 5 V and the voltage of 12.5 V, selectively, to the memory cell transistor in accordance with the operation mode, level shift circuits 15 are provided between a row decoder 11 and a non-volatile memory cell array 13. The level shift circuits 15 are connected to word lines WL1 to WL4 which are connected to the control gates of memory cell transistors MC1 to MC4 in the cell array 13.
A power source voltage Vcc of 5 V is supplied from outside to each level shift circuit 15 in the data read mode, while a power source voltage Vpp of 12.5 V is supplied from outside to each level shift circuit 15 in the programming mode. Consequently, when the word line WL1, for example, is selected by row decoder 11 which decodes row address signals AD0 and AD1, the level shift circuit 15 sets the potential of the word line WL1 to 5 V in the data readout mode, and to 12.5 V in the programming mode. Thus, the control gate of memory cell transistor MC1 is supplied with the voltage of 5 V in the data readout mode and with the voltage of 12.5 V in the programming mode.
When the memory device of FIG. 1 is integrated on a single chip, the distance L1 between adjacent word lines WL1 to WL4 is determined, depending on the size of each of the memory cell transistors MC1 to MC4, the size of each of the AND gates G1 to G4 in row decoder 11, and the size of each of the elements constituting the level shift circuits 15.
In general, the size of each element used in the level shift circuits 15 is greater than that of each of the AND gates G1 to G4 of row decoder 11 and that of each of memory cell transistors MC1 to MC4. Thus, the distance L1 between word lines is determined by the size of each element constituting the level shift circuits 15.
As a result, the distance L1 in the non-volatile memory device becomes greater, compared to a dynamic RAM or the like, which does not require the provision of level shift circuits 15. Normally, a large number of word lines are provided in a non-volatile memory device, therefore the increase in the distance L1 between word lines would prevent high integration of the non-volatile memory device.
Furthermore, when a circuit pattern is laid out in the non-volatile memory device, as shown in FIG. 1, a space for installation of level shift circuits 15 must be provided between the row decoder 11 and the memory cell array 13. This limitation to the layout of the circuit pattern is also a factor preventing high integration of the non-volatile memory device.